1. Field of the Invention
The invention relates to a wave shaping circuit of a semiconductor device testing apparatus, and particularly, to a wave shaping circuit for ultimate waveforms in a waveform generating circuit of the semiconductor device testing apparatus, for applying a pattern waveform to a plurality of semiconductor devices under test.
2. Prior Art
A wave shaping circuit of a conventional semiconductor device testing apparatus has an arrangement as shown in FIG. 3 by way of example.
The wave shaping circuit comprises a modulation waveform generator h, buffer circuits e1, and e2, variable delay circuits a11.about.a1n, and a21.about.a2n, differential circuits b11.about.b1n, and b21.about.b2n, and wave shaping SR registers, e.g. SR flip-flop c1.about.cn.
In these circuits, the modulation waveform generator h generates a set signal S and a reset signal R, inputting the set signal S to the buffer circuit e1 while inputting the reset signal R to the buffer circuit e2.
The buffer circuits e1 and e2 output n-fold signals S1'.about.Sn', and R1'.about.Rn', respectively, whereupon the n-fold signals S1'.about.Sn', and R1'.about.Rn' are inputted to the differential circuits b11.about.b1n, and b21.about.b1n, respectively, via the variable delay circuits a11.about.a1n, and a21.about.a2n, causing output signals therefrom S1.about.Sn, and R1.about.Rn, respectively, to be inputted to the wave shaping registers c1.about.cn.
This enables adjustment of rising and falling, respectively, of pattern waveforms Q1.about.Qn to be applied to semiconductor devices (not shown) under test.
The conventional technology as shown in FIG. 3, however, has the following problems.
More specifically, with the semiconductor device testing apparatus, measurement is performed on a plurality of semiconductor devices under test simultaneously instead of on a single semiconductor device to enhance measurement efficiency.
In this case, according as the number of pins of the devices under test, and the number of the devices under test increase, the number of the modulation waveform generators h increase along with the number of the buffer circuits e1, and e2, respectively.
Consequently, in the conventional arrangement as shown in FIG. 3, transmission paths for signals from the modulation waveform generator h to the wave shaping SR resistors c1.about.cn become longer in length, increasing deviation in timing between the signals S1.about.Sn and the signals R1.about.Rn which are inputted to the wave shaping SR registers c1.about.cn, respectively.
For example, the signal R1 inputted to the wave shaping SR registers c1 is obtained by inputting the signal R generated in the modulation waveform generator h to the buffer circuit e2, and by transmitting the signal R1 obtained therefrom via the variable delay circuit a21 and the differential circuit b21.
Accordingly, as is obvious from FIG. 3, a transmission path for the signal R1 from the modulation waveform generator h to the wave shaping SR register c1 is longer than that for the other signal S1, resulting in large discrepancy in timing between the signals S1 and R1.
Such discrepancy needs to be minimized as much as possible due to a demand for high precision in timing accompanying speed-up in operation of devices under test.
Furthermore, the larger the magnitude of deviation in the timing, the greater the scales of the variable delay circuits a11.about.a1n, and a21.about.a2n become to compensate for the deviation.
In addition, as shown in the figure, as two connecting lines are required between the modulation waveform generator h and the buffer circuits e1 and e2, one for the set signal S and the other for the reset signal R, the number of the connecting lines needs to be further increased in case that a plurality of the modulation waveform generators h are required.